Integrated circuits (ICs) are used in a wide range of electronic devices produced by a large number of manufactures. ICs are seldom manufactured (fabricated) by the system manufacturer, or the electronic device designer. Instead, ICs are manufactured by an IC foundry to the specifications of the electronic device designer and assembled by the system manufacturer.
Recently, a new type of integrated circuit system has been proposed, which is known as a composable system-in-package (SIP) in which a plurality of semiconductor die are attached to a substrate. For example, the substrate can support one or more user-configured “base platform” die and a plurality of standard product die, referred to as peripheral die or “sidecars”.
Examples of composable SIPs are described in greater detail in U.S. application Ser. No. 11/079,028, filed Mar. 14, 2005, and entitled “COMPOSABLE SYSTEM-IN-PACKAGE INTEGRATED CIRCUITS AND PROCESS OF COMPOSING THE SAME” and U.S. application Ser. No. 11/079,439, filed Mar. 14, 2005, and entitled “BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING SAME,” and assigned to the same Assignee as the present application.
The interconnect pattern on the substrate provides signal and power interconnections between the various die that are attached to the substrate and to external devices. The electrical connections to the die are typically made to contact pads on the surfaces of the die that are attached to the substrate.
When composing an SIP, the available technologies have limitations in pitch and interconnection densities. One of the major factors driving a wider pitch of interconnect between the several die in the package is the precision at which the die can be placed relative to each other on the substrate. The substrate must make connections from the base die to one or more of the peripheral die. Connections can also made from each die to the boundaries of the package.
The contact pads on each die define the points on the die to which the electrical interconnections are fabricated on the substrate. However when the die are attached to the substrate, they can be attached with an accuracy that is ±X, ±Y and ±θ, where X and Y represent distance along orthogonal X and Y axes relative to some origin and θ represents orientation or rotation about the origin. When the interconnect pattern is built up in the substrate, the features of the interconnect need to accommodate the variance of die placement and thus, contact pad location. Otherwise, the interconnect pattern will fail to make the necessary interconnections. Placement accuracy can therefore dictate the pad size and pitch on the die and resulting interconnect densities.
With existing approaches, the pad size and pitch dimensions are the same for all of the die in an SIP. The features of the substrate interconnect pattern are defined within a frame of reference that spreads the placement error over all of the die and the substrate. This drives a fixed contact pitch to all of the die in the SIP.
An improved alignment structure and method of manufacturing interconnects in integrated circuit systems are therefore desired, which allow for finer pitch and interconnect densities.
The present invention provides solutions to these and other problems and offers other advantages over the prior art.